The present invention relates to a semiconductor device and a semiconductor integrated circuit device, and particularly to a high-speed writing technique useful for dynamic RAM (random access memory) which operates at a low voltage.
Japanese Patent Unexamined Publication No.Hei 10(1998)-200073 which pertains to dynamic RAM (DRAM) discloses various examples of the relation among the power voltage, data line voltage levels, main word line voltage levels, peripheral circuit voltage levels, and sub word line voltage levels.
Japanese Patent Unexamined Publication No.Hei 9(1997)180436, which corresponds to U.S. Pat. No. 5,774,407, discloses a technique for the transition of the bit line select signal of DRAM between Vss and Vpp.
Japanese Patent Unexamined Publication No.Hei 2(1990)-244756 discloses a technique for the transition of the bit line signal between 2.2 V and 2.8 V and of the column select signal between 0 V and 5 V.
Japanese Patent Unexamined Publication No.Hei 3(1991)-147595 discloses a semiconductor memory which uses bipolar transistors as transistors connected between the bit lines and the sense amplifiers.
Semiconductor integrated circuit devices have their stated interface voltage retained typically at 3.3 V, whereas MOSFETs have lower withstand voltages in the course of progress of higher density integration, and there is a definite trend of the lower internal power voltage of LSI (large-scale integrated circuit) devices. An example of dynamic RAM having its internal power voltage lowered is described in Japanese Patent Unexamined Publication No.Hei 8(1996)-31171, which corresponds to U.S. Pat. No. 5,673,232.
In case the power voltage is relatively high around 3.3 V, the dynamic RAM has its operation speed determined from the read time of the sense amplifier, i.e., the time expended for amplifying a low signal voltage read out of a memory cell to a signal voltage which is as high as the power voltage. However, the study conducted by the inventors of the present invention has revealed that when the power voltage (vdd) is lowered to 1.8 V, the write operation becomes slower than the read operation, and if it is more lowered to 1.0 V that is about the lower limit of operation voltage of the CMOS circuit, the write operation can no more take place.
An object of the present invention is to provide a semiconductor integrated circuit device having a dynamic RAM which is capable of retaining the operational margin and achieving the speed-up at a low operation voltage.
Among the affairs of the present invention disclosed in this specification, representatives are summarized as follows. A semiconductor integrated circuit device includes sense amplifiers each formed of a latch circuit consisting of MOSFETs (or MISFETs) of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair (data line pair) connected with a plurality of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a second bit line pair (signal transfer line pair) provided commonly to a plurality of the first bit line pair in response to the reception of the select signal, and the switching MOSFETs are designed to have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs the first conductivity type of the latch circuits and the select signal is designed to have its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.
These and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.